This invention relates in general to a semiconductor device and a method of fabricating it and, more particularly, to a semiconductor device with local interconnects that are fully self-aligned with respect to a gate section, and a method of making such device.
In one known type of integrated circuit, fabrication of a metal oxide semiconductor field effect transistor (MOSFET) is carried out in the following manner. A p-type silicon substrate has spaced n+ type source and drain regions formed adjacent an upper surface of the substrate. The source and drain regions have respective upwardly facing surface portions thereon, which are each a respective portion of the overall upper surface of the substrate. A gate section is formed to project upwardly from a location between the surface portions which are on the source and drain regions. The gate section includes a gate dielectric layer disposed on the substrate, a gate electrode disposed on the gate dielectric layer, and an insulating layer disposed on the gate electrode. Insulating sidewalls are provided on opposite sides of the gate dielectric layer, gate electrode and insulating layer. A dielectric layer is formed over the substrate and gate section, with an upper surface which is at a level higher than the upper end of the gate section.
Then, in order to create local interconnects to the source and drain regions, a patterned etch is carried out using a selective etching technique, with an etch mask that includes two spaced etch regions which each correspond to a respective one of the source region and drain region. During etching, each etch region results in the creation of a respective recess extending downwardly through the dielectric layer to the surface portion on top of one of the source region or drain region. Subsequently, a layer of a conductive material is deposited on the device in order to fill the recesses, and then is planarized to the top of the dielectric layer, so that the portions of the conductive material which remain in the recesses serve as local interconnects for the source and drain regions.
A consideration involved in using this known fabrication technique is that it is very difficult to precisely align the etch mask with the device, in particular so that the two etch regions are each properly positioned over a respective one of the source and drain regions. This difficulty is due in part to the fact that the level of integration has been progressively increasing over recent years, but alignment techniques do not scale the same as the actual circuit geometry, because alignment techniques involve mechanical considerations, whereas scaling of the circuit geometry involves optical considerations. These considerations affect the spacing between the two etch regions. It would ideally be desirable that the two etch regions be spaced by a distance equal to the width of the gate section so that, in a situation where the two etch regions both happen to be properly positioned, the adjacent sides of the etch regions would each be disposed directly above a respective side edge of the gate section, and the resulting recesses would each be immediately adjacent the gate section with no intervening dielectric material. In actual practice, however, due to potential problems associated with possible mispositioning, the two etch regions have between them a spacing which is somewhat greater than the width of the gate section. Thus, in a situation where these two etch regions both happen to be properly positioned, the adjacent sides of the etch regions will each be disposed a small distance outwardly from a respective side edge of the gate section, and the two resulting recesses will each be spaced a small distance from the gate section, with some dielectric material between each recess and the gate section.
Usually, of course, the two etch regions are not perfectly positioned with respect to the gate section, because there is a physical offset between the actual position and the desired position of the mask relative to the device. Consequently, when the offset is present, one of the two etch regions will typically have an edge portion that overlaps slightly with the gate section, and the other etch region will be spaced slightly from the gate section. As a result, one of the resulting recesses will be immediately adjacent the gate section, whereas the other will be spaced slightly from the gate section with intervening dielectric material.
In order to compensate for such an offset in the etch mask, and the added spacing between the etch regions, while ensuring that the necessary contact area exists between each local interconnect and the associated source or drain region, the known process fabricates each of the source and drain regions with a size which is larger than would otherwise be necessary. In an integrated circuit with a number of such MOSFET devices, the overall integrated circuit must be somewhat larger than if the source and drain regions were of ideal size, and for example may be as much as 15% to 25% larger. This in turn results in the integrated circuit having a lower circuit density than would be desirable. Moreover, since each of the source and drain regions are larger than necessary, the result is larger junction areas, larger junction capacitances, larger junction leakage currents, and larger source and drain resistances. Consequently, while this known technique for forming local interconnects has been generally adequate for its intended purposes, it has not been satisfactory in all respects.
From the foregoing, it may be appreciated that a need has arisen for an integrated circuit having two local interconnects that are self-aligned with respect to a section of the device which is disposed between them so as to permit a reduction in the size of the integrated circuit, and a method of making such a device.
According to one form of the present invention, a method is provided to address this need, and involves: fabricating a structure that has laterally spaced first and second sections with respective upwardly facing first and second surface portions thereon, and that has a third section projecting upwardly beyond each of the first and second surface portions from a location therebetween; forming on the structure an insulating layer which has portions disposed over the first and second surface portions, the third section extending into the insulating layer; effecting a patterned etching of an upper side of the insulating layer using an etch pattern, the etch pattern including an etch region which extends from a location disposed over the first surface portion to a location disposed over the second surface portion, wherein etching in the etch region creates first and second recess portions which respectively extend downwardly through the insulating layer toward the first and second surface portions on opposite sides of the third section; depositing a conductive material into the first and second recess portions; and planarizing an upper side of the device to a level corresponding to an upper end portion of the third section.
According to another form of the present invention, an apparatus is provided to address the need discussed above, and includes: laterally spaced first and second sections with respective upwardly facing first and second surface portions thereon; a third section projecting upwardly beyond each of the first and second surface portions from a location therebetween; an insulating layer which has portions disposed over the first and second surface portions, the third section extending into the insulating layer, and the insulating layer having first and second recess portions which respectively extend downwardly through the insulating layer toward the first and second surface portions on opposite sides of the third section, each such recess portion being immediately adjacent a respective side of the third section and having therein a conductive material.